We use a system based on OpenAmp with Linux running on CPU0 (L1+L2 cache) and FreeRTOS on CPU1 (only L1 cache).
I'm a bit in doubt regarding MMU table configuration on CPU1.
The shared bit enables cache coherency between L1 caches and L2 cache. We don't use this.
We see the DDR as single point of truth for shared data (small volume, preprocessed on CPU1 side or provided via IP cores / DMA) and notify the other system after flushing the cache.
Are these setting correct to have CPU1 isolated from all coherency mechanisms?
Tex 2:0 C B
000 0 0 - Strongly ordered (peripherals)
001 0 0 - Non cached memory
100 c1 b1 - Cached memory (L1 cache only)
When I said cache lockdown, it means that some L2 cache ways could be configured in a way that the cache way can only perform cache allocation for one CPU's access. But the allocated cache can still be accessed by other CPUs.