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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    【Cortex-M4 with STM32F412RG】 0

    • Cortex-M
    • CMSIS
    • Cortex-M4
    • STM32 F4
    3546 views
    4 replies
    Latest over 4 years ago
    by Kieron Kotaroh Nakamura
  • Suggested Answer

    Getting started programming for stm32f103c8t6 board as an absolute beginner 0

    3567 views
    6 replies
    Latest over 4 years ago
    by Andy Neil
  • Answered

    Setting breakpoints at runtime and stepping on the Cortex A53. 0

    6032 views
    9 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Self hosted debug on Cortex A53, setting up a breakpoint to cause an exception. 0

    2974 views
    1 reply
    Latest over 4 years ago
    by KelvinInIdaho
  • Not Answered

    Cortex-A53 : complex array problem 0

    • Cortex-A53
    • Cortex-A9
    3132 views
    2 replies
    Latest over 4 years ago
    by BatuhanBulut
  • Answered

    How does cortex-M33, for example, know previous exception priority? 0

    2749 views
    4 replies
    Latest over 4 years ago
    by Susumu Endoh
  • Not Answered

    Where to download IOTKit_CM33_MPS3 FPGA image? 0

    1078 views
    0 replies
    Started over 4 years ago
    by ziming
  • Not Answered

    Error when using Cortex -M3 DesignStart FPGA-Xilinx edition 0

    • FPGA Xilinx
    • Cortex-M3
    • DesignStart
    2111 views
    0 replies
    Started over 4 years ago
    by Shiping
  • Not Answered

    Cortex A-35 cache L2 content access +1

    10968 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    What is the execution priority inside WFI for CortexM4? 0

    • Architecture
    • Cortex-M4
    3840 views
    4 replies
    Latest over 4 years ago
    by Jayden Huang
  • Answered

    How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted? 0

    • AXI
    21371 views
    5 replies
    Latest over 4 years ago
    by Eric KIM
  • Answered

    Is Advanced-SIMD supported in Cortex-R5F? 0

    • Cortex-R
    • Cortex-R5
    • Armv7-R
    • SIMD and Vector Execution
    12269 views
    5 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Asynchronous External abort 0

    3982 views
    3 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    coherence between R82 and other cpu or hardware modules 0

    • cortex-r8
    2965 views
    4 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Reduced Virtual Interrupt Controller RVIC 0

    8053 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Suggested Answer

    CMSIS Core legacy Version 0

    3241 views
    6 replies
    Latest over 4 years ago
    by Andy Neil
  • Not Answered

    Fixed burst and AxLEN relationship 0

    19834 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception 0

    • Real Time Operating Systems (RTOS)
    • Trusted Firmware-M
    • TrustZone for Armv8-M
    • Armv8-M
    6466 views
    3 replies
    Latest over 4 years ago
    by Michael Jung
  • Not Answered

    Understanding Linker Map function addresses for Thumb code in Keil uVision 0

    • Keil
    • uVision
    • Arm MAP
    • Debugging
    • Cortex-M4
    2306 views
    0 replies
    Started over 4 years ago
    by Michael Hul
  • Answered

    Porting between different Vendors 0

    3145 views
    4 replies
    Latest over 4 years ago
    by Andy Neil
<>
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