Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    cant write to APSR register cortex-M23 +1

    • Cortex-M23
    1228 views
    1 reply
    Latest over 2 years ago
    by MohSa
  • Not Answered

    GIC600AE - GICA frames: Registers for message-based Interrupts 0

    • pcie
    • GICv2
    • GICv3/v4
    1196 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Default Memory Attribute with Cortex-A7 on memory space and disabled MMU 0

    1639 views
    2 replies
    Latest over 2 years ago
    by Stephan Cadene
  • Not Answered

    CA715 with CHI version 0

    1135 views
    1 reply
    Latest over 2 years ago
    by Brent Lui
  • Not Answered

    what could be best DIY arm controller or processor for AI-vision 0

    1329 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    Page tables using LPAE 0

    2098 views
    2 replies
    Latest over 2 years ago
    by jboulos
  • Answered

    GICv3: Purpose of EOIcount in ICH_HCR_EL2 and LRENPIE maintenance interrupt 0

    2770 views
    9 replies
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    memory copy using ARM NEON does not better than memcpy (a little improvement) 0

    • SIMD and Vector Execution
    2923 views
    0 replies
    Started over 2 years ago
    by soojin
  • Suggested Answer

    ARM CoreLink™︎ SMC-35x AXI Static Memory Controller Series IP 0

    • Microcontroller (MCU)
    • CoreLink SMC-35x AXI Series
    1760 views
    3 replies
    Latest over 2 years ago
    by MCU lover
  • Suggested Answer

    Is that ok to use neon instructions over vfp ? 0

    1300 views
    1 reply
    Latest over 2 years ago
    by hoover90017
  • Not Answered

    What are the most tangible differences between an SSD controller with Cortex-R8 and Cortex-R5? 0

    1647 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    ARM CoreLink™︎ SMC-35x AXI Static Memory Controller Series IP 0

    • Microcontroller (MCU)
    • Static Memory Controllers
    1261 views
    1 reply
    Latest over 2 years ago
    by MCU lover
  • Not Answered

    How does cache system work when Dual-Core Lockstep mode in Cortex-A76AE is activated. 0

    • Cortex-A76AE
    1336 views
    1 reply
    Latest over 2 years ago
    by Yiming Gan
  • Suggested Answer

    AXI5 : Read data chunking 0

    2727 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AXI5 Atomic compare 0

    1522 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    CA55 snoop response behavior when cache line is clean 0

    1073 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Mapping MIDR PartNum to ARM Core Type 0

    2543 views
    3 replies
    Latest over 2 years ago
    by Dennis Chang
  • Not Answered

    The arm developer can't download 0

    1475 views
    2 replies
    Latest over 2 years ago
    by fish man
  • Suggested Answer

    CA55 snoop response behavior when cache line is clean 0

    1835 views
    2 replies
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Assembly encoding that triggers an exception in both the A32 and T32 instruction set 0

    1113 views
    2 replies
    Latest over 2 years ago
    by Rosario
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone