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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3640 Questions
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  • Not Answered

    HN-I error of CCN-504 0

    719 views
    0 replies
    Started over 3 years ago
    by Harvey-Lin
  • Not Answered

    HN-I error of CCN-504 0

    723 views
    0 replies
    Started over 3 years ago
    by Harvey-Lin
  • Not Answered

    TCM Gate Unit 0

    1135 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Suggested Answer

    ARM SVE2 instruction to use 2048 bits vector 0

    • Fixed Virtual Platforms (FVPs)
    • Neoverse
    3984 views
    5 replies
    Latest over 3 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Bit-shift Integer Rounding-to-even with ARMv8 NEON SIMD on Aarch64 0

    • NEON
    1482 views
    0 replies
    Started over 3 years ago
    by Prem_DawnDigitech
  • Not Answered

    What information is included in cortex R52 trace 0

    • ETM
    • Cortex-R52
    • CoreSight Debug and Trace
    • AMBA 3 ATB Interface
    1505 views
    0 replies
    Started over 3 years ago
    by hello_me
  • Not Answered

    PC value becomes X in Cortex R5 0

    • R5
    • Cortex-R5
    • R8
    • cortex-r8
    1292 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    operating system 0

    • operating systems
    1334 views
    2 replies
    Latest over 3 years ago
    by SBR_123
  • Not Answered

    Question about invalidate queue in ARM cache. 0

    1161 views
    0 replies
    Started over 3 years ago
    by steven~~~s
  • Answered

    Why the dummy cycles needed for every APB transfer 0

    4792 views
    5 replies
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Runtime detection of SVE2 not working as expected 0

    • SVE
    4057 views
    2 replies
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Justification for write-back of UniqueClean line for WriteEvictFull CHI opcode. +1

    • AMBA 5 CHI
    2596 views
    2 replies
    Latest over 3 years ago
    by nizam.ahmed
  • Not Answered

    ARMv7 TLB dump decoding 0

    • Armv7-A
    • Cortex-A5
    2106 views
    2 replies
    Latest over 3 years ago
    by Strong
  • Not Answered

    Unrolling a loop 0

    • Cortex-A53
    1405 views
    2 replies
    Latest over 3 years ago
    by Zvi Vered
  • Suggested Answer

    ARMv8-A Cortex-A72: Generic timer is backoff 0

    • Cortex-A72
    • Armv8-A
    3301 views
    1 reply
    Latest over 3 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    Reverse engineering ARM firmware: selecting an architecture with a superset of features when importing ARMv7/ARMv8 firmware into Ghidra +1

    6510 views
    1 reply
    Latest over 3 years ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    [ACE] Why CleanUnique must write back to memory? 0

    2543 views
    1 reply
    Latest over 3 years ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Unaligned memory access fault with STRH on Cortex-M7 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    3090 views
    5 replies
    Latest over 3 years ago
    by alexxs88
  • Answered

    M0 SPI outputting 16bit not 8bit 0

    • Cortex-M0
    1499 views
    1 reply
    Latest over 3 years ago
    by MikeH32096
  • Not Answered

    STM32F103 - Switching from JTAG to SWD 0

    • SWD
    1829 views
    0 replies
    Started over 3 years ago
    by SamPfarrer
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