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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3600 Questions
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  • Not Answered

    Regarding the order of interrupt requests 0

    • Interrupt Handling
    • Cortex-M4
    667 views
    0 replies
    Started over 1 year ago
    by Makoto Satou
  • Answered

    Is Arm Core PMU and DSU_PMU the same hardware component? 0

    • DSU-120
    • Cortex-A
    • pmu-dsu
    • Cortex-A720
    1379 views
    1 reply
    Latest over 1 year ago
    by Michael Williams Arm Employee Badge
  • Suggested Answer

    How does the Cortex M0+ pipeline handle a branch instruction to an address that is not 32-bit aligned? 0

    • Pipeline Control and Execution
    • Cortex-M0+
    1514 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    M-profile Vector Extension (MVE) intrinsics VS Advanced SIMD (Neon) intrinsics, Similar? 0

    • MVE Intrinsics
    • NEON
    • MVE
    • Cortex-A
    • Cortex-M
    1377 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    MHU v2.1 - R2NR interrupt 0

    951 views
    0 replies
    Started over 1 year ago
    by GMH
  • Answered

    Is M-Profile Vector Extension (MVE) available only in Cortex-M55? 0

    • Architecture
    • MVE Intrinsics
    • MVE
    • Cortex-M
    1240 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    [GIC-500v][ARMv8][A72] why SGI0 can't be triggered twice in validation test? 0

    • Cortex-A72
    • Interrupt Handling
    • AArch64
    • GICv3/v4
    • Armv8-A
    • Cortex-A
    • Interrupt
    2155 views
    4 replies
    Latest over 1 year ago
    by Kael Hong
  • Not Answered

    Disable all H/W prefetchers on ARM Cortex A-57 0

    2606 views
    4 replies
    Latest over 1 year ago
    by ShikharJain
  • Suggested Answer

    Data cache and I cache Memory allocation 0

    1258 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    STM32H7 question: ARM cortex M7 intrinsics emulation on x86 PC ? 0

    • Cortex-M7
    • intrinsics
    • simd
    1820 views
    2 replies
    Latest over 1 year ago
    by Laurent M
  • Answered

    How is the register CDBGDCD_EL3 encoded? +1

    1251 views
    1 reply
    Latest over 1 year ago
    by User_0182
  • Answered

    Question about definition in armv8 memory model 0

    • Armv8-A
    • Memory
    1904 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    HART-I910 DATASHEET 0

    2595 views
    2 replies
    Latest over 1 year ago
    by Geovani Barbosa
  • Not Answered

    Cortex M0 Processor Design start Syntax error 0

    755 views
    0 replies
    Started over 1 year ago
    by WooTaek Song
  • Answered

    RetToSrc value for Snoop opcodes contradicting in AMBA CHI - 5E.c 0

    1709 views
    2 replies
    Latest over 1 year ago
    by Nachiket Acharya
  • Not Answered

    ARM A76 (RK3588S)Stp Instruction take a long time 0

    • Cortex-A76
    • Armv8-A
    • rk3588s
    • stp
    • Software Development
    • Instruction Scheduling/Issue
    1126 views
    1 reply
    Latest over 1 year ago
    by PMU_study
  • Not Answered

    Is this procedure to get A53 to read/write (test) the L1D cache feasible. 0

    769 views
    0 replies
    Started over 1 year ago
    by User_0182
  • Answered

    cortex-m3 cycle model +1

    • Cycle Models
    • Cortex-M3
    • License Management
    1243 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Does Cortex-R8 support Coresight SoC-600? 0

    1457 views
    1 reply
    Latest over 1 year ago
    by Stuart Hirons Arm Employee Badge
  • Answered

    R5F mbif file +1

    1810 views
    2 replies
    Latest over 1 year ago
    by Junkai Sun
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