axi stream synchronous reset and Questa QVIP assertion checker

I need help with the interpretation of this statement within the axi stream protocol spec -

2.8.2 Reset

ARESETn is a single, active-LOW reset signal. The reset signal can be asserted asynchronously, but deassertion
must be synchronous after the rising edge of ACLK.
During reset, TVALID must be driven LOW. All other signals can be driven to any value.

I'm doing verification work where Questa QVIP assertion checker flags the synchronous reset timing as error because it doesn't adhere to the "asserted asynchronously" part of this statement. The RTL implements synchronous reset assertion because of FPGA guidelines. As I see it, the rule "can be" doesn't necessarily exclude usage of synchronous reset assertion. Is rule actually strict in adherence to the asynchronous assertion or can it allow for synchronous assertion?