L2 Cache ECC Notification

I am trying to implement L2 ECC for A72 core and its notification. 

What I have understood, L2 ECC can be enabled using L2CTLR_EL1 register.

And L2 ECC system generates two error signals

nEXTERRIRQ and nINTERRIRQ,

I assume , nINTERRIRQ will be generated in case of double bit error.

Could you help me, if there is some notification for single bit correctable error, which is done by L2 ECC block

or say, in case some single bit correction done, How CPU will know