Hello
I'm facing a problem that the core runs on the NVM at first, then jump to the RAM code to do some operation for the same partition of the NVM. After the operation (code on the RAM) is completed, back the NVM for the following code execution. In the RAM code, the completion of the NVM operation is ensured by checking some status flag.
The Read-While-Write error for the NVM occurs when branch predictor (IMP_BPCTLR) is enabled, I/D cache disabled, instruction speculative access disable (ISPECDIS = 1) and instruction prefetch disabled (L1IPFCTL = 0).
Only when branch predictor (IMP_BPCTLR) is disabled, the RWW error would not happen.
Could you explain how the branch predictor in the Cortex-R52+ work to help us on the root cause analysis ?
Do the IMP_BPCTLR affect the return address prediction, like pop {... pc} ?
Thanks and regards, Grace
I think the branch predictor is a symptom rather than the cause of the problem. The architecture allows for speculative data accesses to any region marked as Normal and speculative instruction fetch to any region marked as executable. If you have a region that for some reason should not be speculatively accessed, then you need to mark it as Device and execute never (XN).
For your example I'd expect a sequence similar to this:
Hi Martin
So you think the speculative accesses to the NVM results in the issue ? At first, I thought so but I disabled the speculative access for R52+, the issue was still there.
About the branch predictor, when prediction happened, does the predicted instruction fetched from the memory to the prefetch buffer ?
BR, Grace
I'm not an expert on the Cortex-R52+, so I can't really comment on what the control you're setting does. But most processors will do a variety of different kinds of speculation and prefetch. It's possible that control disables a specific class/type of speculative accesses.
Grace WANG said:About the branch predictor, when prediction happened, does the predicted instruction fetched from the memory to the prefetch buffer ?
Essentially, yes. If the processor sees a branch coming it will attempt to predict whether the branch will be taken, and if so, predict what location to prefetch from.
In your case, it could be a mis-predict leading to a fetch from NVM. Or, it could be a "correct" prediction, but the prefetch is happening sooner than you expect - meaning it occurs before the NVM is ready. It could also be nothing to do with branch prediction, and it's just that turning off branch prediction changes the timing.
Either way, the correct/safe thing to do if you have a region that should not be speculatively accessed is configure the MPU regions accordingly. That means mark as Device (or no access) to prevent data speculation, XN (or no access) to prevent instruction prefetching.