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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3587 Questions
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  • Not Answered

    What is TrustZone for ARMv8-M? 0

    • CHI
    • Security
    • Cortex-M3
    • Cortex-A
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Software Development
    12688 views
    0 replies
    Started over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Answered

    Linker in gnu arm toolchain says "group ended without start" thought there is no such option in my build +1

    • Toolchain
    • Embedded Software
    • GCC
    • Thumb
    • GNU Arm
    • Cortex-M
    • Cortex-M4
    8924 views
    5 replies
    Latest over 8 years ago
    by Thomas Preudhomme Arm Employee Badge
  • Suggested Answer

    Cortex A53 Program Counter Load After Debug Exit 0

    6473 views
    2 replies
    Latest over 8 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Is there an atomic way to enable the MMU and continue at a given virtual address +1

    4617 views
    1 reply
    Latest over 8 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    What's happening if NMI is active (via a push-button) during µC (Cortex M4) start-up (power on)? +2

    • Cortex-M
    • Cortex-M4
    7812 views
    3 replies
    Latest over 8 years ago
    by Jerome Decamps - 杜尚杰
  • Suggested Answer

    What's implemented in STM32F103C8? 0

    5022 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    thumb 2 instruction set 0

    12344 views
    7 replies
    Latest over 8 years ago
    by cray
  • Suggested Answer

    Can Cortex M7 AXI master interface generate interleaved writes to the same slave? 0

    5008 views
    3 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    What does the assertion "AXI_ERRS_BRESP_ALL_DONE_EOS" in "AMBA 3 AXI Protocol Checker User Guide" mean? 0

    4815 views
    2 replies
    Latest over 8 years ago
    by Diandian Zhang
  • Answered

    Delay Subroutine LPC2148 Assembly +1

    • Arm7
    • GPIO
    • Arm Assembly Language (ASM)
    12512 views
    3 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Not Answered

    ARM Cortex Educational Courses 0

    2904 views
    1 reply
    Latest over 8 years ago
    by Mark Nicholson Arm Employee Badge
  • Suggested Answer

    How to make sure L2CC won't make any data write interleave request? 0

    3366 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    armv5TE +1

    • Armv5T
    • Armv5TE
    • Armv5
    7432 views
    3 replies
    Latest over 8 years ago
    by kalle
  • Answered

    when and where will the LDP instruction trigger an exception ? 0

    8867 views
    6 replies
    Latest over 8 years ago
    by daith
  • Not Answered

    Cortex-A8 - accessing banked registers from monitor mode 0

    • Armv7-A
    • Cortex-A
    • Cortex-A8
    • Debugger
    7793 views
    6 replies
    Latest over 8 years ago
    by Nisar
  • Answered

    VTTBR_EL2 alignment 0

    • Armv8-A
    4434 views
    2 replies
    Latest over 8 years ago
    by Vincent Siles
  • Answered

    What is the equivalent instruction for QSUB in ARMv8? 0

    • Armv8
    • Arm Assembly Language (ASM)
    5520 views
    3 replies
    Latest over 8 years ago
    by daith
  • Answered

    ELF entry point in thumb mode (armv7/aarch32) 0

    • Thumb
    • AArch32
    7915 views
    3 replies
    Latest over 8 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    ARMv8-M TrustZone: Secure & Non-Secure Modules Implementation +1

    • Cortex-M23
    • Cortex-M33
    • Armv8-M
    4473 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    IOC flag at FPSCR register +1

    • Cortex-R
    • Cortex-R4
    7673 views
    5 replies
    Latest over 8 years ago
    by hotta
<>
Topics being discussed in this forum
  • AArch64
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