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Architectures and Processors forum Pending interrupt status

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Pending interrupt status

Karolis over 7 years ago

Hello,

If there is a pending interrupt status already set, but it is not being handeled yet, is it possible that somehow that interrupt will no longer have pending status (pending status will disappear) until it is processed and no processing will happen after that because no pending status? What cases might cause that? If interrupt causing conditions restore it should not reset pending status, yes?

This question pasrticularry applies for Cortex M CPUs, but information on A profile ir appreciated as well.

Also, please share official documwntation if it covers this case.

Thank you in advance.

+1 Martin Weidmann over 7 years ago

I'm not an M class expert. However, there are a lot of similarities between the GIC and NVIC...

In GIC, an interrupt must be configured as either level-sensitive or edge-triggered. The answer depends on which the interrupt source is configured as:
* Level-sensitive, an interrupt would cease to be pending if the source de-asserted the signal.
* Edge-triggered, software would have to write the appropriate GICD_ICPENDR<n> (Clearing Pending State) register to remove the pending state.

Note: It would be unusual for a level-sensitive peripheral to de-assert the interrupt signal without software interaction.
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+1 Peter Rielly over 7 years ago in reply to Martin Weidmann

In the M-class NVIC the interrupt pending state latches on the rising edge of the interrupt line; so deasserting the signal will not cause the interrupt to leave the pending state.

Software can manually change the pending state in the same way as the A-class GIC using one of the CLRPENDx registers.
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