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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3586 Questions
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  • Not Answered

    maximum level of functions than can be called within 0

    • Cortex-M3
    • Cortex-M
    4339 views
    5 replies
    Latest over 9 years ago
    by NABEEN LAL AMATYA
  • Answered

    Memory protection unit - Cortex-M4 0

    • Cortex-M
    • Cortex-M4
    6719 views
    2 replies
    Latest over 9 years ago
    by Matic
  • Not Answered

    Code optimization for a Samsung S5P6818 Octa-Core Cortex-A53, 400M Hz - 1.4G Hz 0

    • Cortex-A53
    • Cortex-A
    11245 views
    6 replies
    Latest over 9 years ago
    by Carlos Delfino
  • Answered

    Usefulness of MPU in a non-OS system 0

    • Cortex-M
    • Cortex-M4
    6511 views
    4 replies
    Latest over 9 years ago
    by Matic
  • Not Answered

    VTOR: offset address configuration 0

    • Cortex-M
    • Cortex-M4
    6059 views
    2 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Not Answered

    Performance effect because of removing some instructions from ARMv8? 0

    • Cortex-A72
    • 32-bit
    • Armv7
    • Cortex-A15
    • Armv8
    • Cortex-A
    11619 views
    7 replies
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    SIGILL in 32bit chroot on Cortex-A57 0

    • Armv6
    • Cortex-A57
    • Cortex-A
    5151 views
    1 reply
    Latest over 9 years ago
    by Yichao Yu
  • Answered

    Cortex A9 single core 0

    • Cortex-A9
    • Cache
    • Memory Management Unit (MMU)
    • Cortex-A
    7071 views
    5 replies
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Alignment in ARM? +1

    • Cortex-M0
    • 32-bit
    • Cortex-M
    • 64-bit
    14081 views
    1 reply
    Latest over 9 years ago
    by daith
  • Answered

    PL310 cache synchronization 0

    • Cortex-A9
    • Cache
    • Cortex-A
    5386 views
    2 replies
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    in arm7tdmi, when FIQ and RIQ occures at same time so how both are executed sequentially,first FIQ and thenIRQ? 0

    • Arm7
    • Cortex-M3
    • Cortex-A
    • Cortex-A7
    • Cortex-M
    17080 views
    12 replies
    Latest over 9 years ago
    by Jens Bauer
  • Answered

    why there are 4 cores per cluster in ARMV8 architecture 0

    • Cortex-A53
    • big.LITTLE
    • Armv8-A
    • Cortex-A
    17358 views
    10 replies
    Latest over 9 years ago
    by 42Bastian
  • Answered

    Is there a list of all opcodes mnemonics understood by each architecture? 0

    • Armv7-A
    • Armv7-R
    • GNU
    • AArch32
    13196 views
    4 replies
    Latest over 9 years ago
    by Myy
  • Answered

    Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit) +1

    • Cortex-M3
    • Memory Protection Unit (MPU)
    • Cortex-M
    • Cortex-M4
    4363 views
    2 replies
    Latest over 9 years ago
    by harshan
  • Not Answered

    Multicore SMP using Linux kernel 0

    • 32-bit
    • Cortex-A9
    • smp
    • Cortex-A
    • multiprocessing
    • Arm Assembly Language
    • Linux
    6796 views
    1 reply
    Latest over 9 years ago
    by Arslan
  • Answered

    pl310 CACHE_ID register 0

    • AMBA
    • Cache
    5270 views
    4 replies
    Latest over 9 years ago
    by Vincent Siles
  • Answered

    Trustzone and caches 0

    • Cache
    • Memory Management Unit (MMU)
    • TrustZone
    • Linux
    6918 views
    1 reply
    Latest over 9 years ago
    by Vincent Siles
  • Answered

    State of link register on an interrupt from Thumb (ARM7TDMI). +1

    • Arm7
    • Thumb
    3324 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Parallelism between CPU and FPU 0

    • Cortex-M7
    • Cortex-M
    • Cortex-M4
    4513 views
    1 reply
    Latest over 9 years ago
    by daith
  • Answered

    Raspberry Pi 2 JTAG error on memory access +1

    • Raspberry Pi
    • Cortex-A
    • Cortex-A7
    • Linux
    5463 views
    1 reply
    Latest over 9 years ago
    by Alessandro
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone