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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3625 Questions
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  • Not Answered

    what is the clock cycles overhead for context switch in trust zone? 0

    • Cortex-M23
    • TrustZone
    • Cortex-M33
    6999 views
    5 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    SPI on STM32F407 Discovery not working 0

    3958 views
    2 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    ldr 6 cycles on M4 from flash ? (and "weird" constant fetched ) 0

    • Cortex-M4
    7885 views
    8 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Why do we have to send HMASTLOCK signal to the slave? 0

    • AHB-Lite
    • Cortex-A
    • AHB
    33240 views
    1 reply
    Latest over 6 years ago
    by Xingguang Feng
  • Not Answered

    SAM D09 SPI Hardware Slave Select 0

    • Microcontroller
    2900 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    CM4 str.w 1 cycle .... 0

    1973 views
    0 replies
    Started over 6 years ago
    by d.ry
  • Not Answered

    IT instruction block question : how does this work .. (block seems always executed) 0

    • Control Flow Instructions
    • Arm Assembly Language (ASM)
    • Cortex-M4
    4335 views
    1 reply
    Latest over 6 years ago
    by d.ry
  • Not Answered

    Limit NSC calls to specified RTOS tasks. 0

    10031 views
    1 reply
    Latest over 6 years ago
    by Ken.Liu Arm Employee Badge
  • Not Answered

    To the Website admin : problem download a resticted non-confidential document 0

    22367 views
    1 reply
    Latest over 6 years ago
    by LATH
  • Not Answered

    Problems with stack pointer when i use my bootloader 0

    4230 views
    1 reply
    Latest over 6 years ago
    by JosepI
  • Not Answered

    Setting up NVIC with ISR in CortexM4 0

    6189 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Audio Using LPC1768 (Cortex M3) 0

    5126 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    DVFS implementation in C 0

    21780 views
    2 replies
    Latest over 6 years ago
    by Mohammed Bey
  • Answered

    EDSCR err bit set after a write to EDITR +1

    • Cortex-A57
    • AArch64
    • Armv8-A
    26925 views
    6 replies
    Latest over 6 years ago
    by kka
  • Not Answered

    Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler 0

    • Armv7-A
    • Armv7 Exception Model
    24826 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Can I enable and use D-Cache with disabled MMU? 0

    30169 views
    4 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    cm7 and cm4 comparison 0

    2706 views
    1 reply
    Latest over 6 years ago
    by Pallavi boreddy
  • Answered

    obtaining cycle count on cortex m7 0

    7536 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    M4 Deep Sleep 0

    • STM32 F4
    5736 views
    2 replies
    Latest over 6 years ago
    by AliRizaDenenPezevenk
  • Answered

    Permission fault, level 2 on MMU enable 0

    • EL1
    • Armv8-A
    • Memory Management Unit (MMU)
    24589 views
    1 reply
    Latest over 6 years ago
    by a.surati
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