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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3600 Questions
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  • Answered

    ARM Cortex-A7 generic timer 0

    • Cortex-A
    • Cortex-A7
    11506 views
    4 replies
    Latest over 10 years ago
    by hostia
  • Answered

    Question about a code snippet on ARM, Thumb state change 0

    • Thumb
    9410 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Is the 'S' necessary in the asm code? 0

    • Cortex-A
    • Cortex-A8
    • C
    5494 views
    5 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    What does it mean 'IT can be omitted'? +1

    • Thumb
    • Cortex-A
    5946 views
    4 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    What type of ARM is used in 10-Gb Ethernet chip? 0

    • Cortex-A57
    • Cortex-A15
    • Cortex-A
    6313 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    How to understand SDIV instruction availability? 0

    • 32-bit
    • Armv7-A
    • Cortex-A15
    • Cortex-A
    • Thumb2
    6707 views
    2 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    How many states for an ARM Cortex A8? 0

    • Thumb
    • Cortex-A
    • Cortex-A8
    • Thumb2
    4975 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    What is P1, P2, P3 and P4 use in Thumb2 IF block instruction? 0

    • Thumb2
    7454 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    Why does ARMSim# not recognize instruction 'addw'? 0

    • Arm7
    • Thumb
    7169 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Fastest way to transpose array in cortex-m4? +1

    • Cortex-M
    • Cortex-M4
    3357 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    indicator for A core system timer implemented or not 0

    • Armv7-A
    • AArch64
    • Armv8-A
    • Armv7-R
    • AArch32
    5846 views
    4 replies
    Latest over 10 years ago
    by hostia
  • Answered

    Cortex-A7 Processor DSP +1

    • Cortex-A
    • Cortex-A7
    6928 views
    5 replies
    Latest over 10 years ago
    by Акоб
  • Answered

    Why does ARM Branch with Link (BL) instruction considers prefetch? +1

    • Thumb
    5066 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARM Cortex A8 : Enabling D Cache aborts 0

    • Cache
    • Cortex-A
    • Cortex-A8
    59807 views
    32 replies
    Latest over 10 years ago
    by Gopu
  • Answered

    What's the difference between core, processor,cluster and CPU in ARM architecture? 0

    • Cortex-A15
    • Cortex-A
    • Cortex-M
    22859 views
    1 reply
    Latest over 10 years ago
    by Alban Rampon
  • Answered

    GIC-500 how connects to CPU cores? +1

    • Cortex-A72
    • Armv8-A
    • Cortex-A
    5808 views
    3 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ? +1

    • Cortex-A
    • Cortex-A7
    5778 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    CNTP_CVAL register write from EL1-NS ("Config-RW") 0

    • Juno Arm Development Platform
    • Armv8-A
    4106 views
    1 reply
    Latest over 10 years ago
    by Sudeep Holla Arm Employee Badge
  • Answered

    In processors supporting TrustZone, how is secure memory access protected from a non- secure world application accessing it? 0

    • 32-bit
    • AXI
    • TrustZone
    15814 views
    3 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Cache maintanance operation to PoC +1

    • Cortex-A9
    • Cache
    • Cortex-A
    • Cortex-A8
    10851 views
    4 replies
    Latest over 10 years ago
    by Luke
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone