Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Not Answered

    Cortex-M33_TZ FuSa and Security assessment report. 0

    • Fusa
    • TrustZone for Armv8-M
    • Cortex-M33
    667 views
    0 replies
    Started over 1 year ago
    by Vishal Rana
  • Answered

    Cortex-R52+ branch predictor 0

    • Cortex-R52
    • branch
    • return stack
    • pop
    • Branch Prediction
    2208 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    STM32F411 code only running when stepped through a debugger 0

    • Debugger
    • Cortex-M4
    • STM32 F4
    3175 views
    6 replies
    Latest over 1 year ago
    by Christopher Theriault
  • Not Answered

    Generic Interrupt Controller Usage 0

    • Agilex-7
    • gic
    • a53
    1449 views
    2 replies
    Latest over 1 year ago
    by Balerion
  • Not Answered

    L2 Cache ECC Notification 0

    • ecc
    • L2
    1542 views
    2 replies
    Latest over 1 year ago
    by uditknit
  • Not Answered

    Running into unexpected behavior with Cache Way Partitioning on the A76/DSU 0

    • Cortex-A
    • DSU
    • DynamIQ Shared Unit (DSU)
    • A76
    1029 views
    0 replies
    Started over 1 year ago
    by Cole Strickler
  • Not Answered

    How to use the Memory Reconstruction Port in Cortex-R series processor? 0

    • Cortex-R52
    • Cortex-R
    • Cortex-R5
    • cortex-r8
    813 views
    0 replies
    Started over 1 year ago
    by junhao.wang
  • Not Answered

    Issuing MakeInvalid from a UD state 0

    • AMBA
    • Cache coherency
    • CHI
    1209 views
    1 reply
    Latest over 1 year ago
    by Nachiket Acharya
  • Suggested Answer

    What is the DHRYSTONE, DMIPS number for GCC compiler fopr M85 core? +1

    1451 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Is the isb necessary between modifying ttbr and flushing TLB? 0

    • Armv8-A
    • Memory Access Instructions
    • Instruction Fetch
    3538 views
    6 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    GICv3 ICC_EOIR 0

    • GICv3/v4
    • Armv8
    • Interrupt
    2733 views
    5 replies
    Latest over 1 year ago
    by Grace WANG
  • Suggested Answer

    Guarantees for undefined and unallocated instruction encodings 0

    • Architecture
    • AArch64
    • Documentation
    • Armv8-A
    3917 views
    8 replies
    Latest over 1 year ago
    by Peter Harris Arm Employee Badge
  • Answered

    Cortex-A9 accessing atomic variable results in dead loop 0

    • Cortex-A9
    • Memory Management Unit (MMU)
    • Cortex-A
    2490 views
    4 replies
    Latest over 1 year ago
    by f zl
  • Answered

    [GIC500v3][ARMv8][A72] Interrupt is not handled correctly after A72 change from EL3 to EL1 +1

    • EL3
    • Armv8-A
    • SGI
    • gic500
    3703 views
    8 replies
    Latest over 1 year ago
    by Kael Hong
  • Suggested Answer

    Expected Increase in Throughput for Int8 vs FP32 Multiplication 0

    • Armv8-A
    • fma
    2666 views
    5 replies
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    IWIC clock in M55 and q-channel clock gating 0

    782 views
    0 replies
    Started over 1 year ago
    by Ygal Berdugo
  • Suggested Answer

    Calling an NS Function from NSCallable Section in TrustZone-M 0

    • TrustZone for Armv8-M
    1398 views
    1 reply
    Latest over 1 year ago
    by Sally Sun Arm Employee Badge
  • Suggested Answer

    Does ECC work only during read/write operation? 0

    • ecc
    1500 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    Device-GRE memory attributes and A53 core lockup 0

    • Cortex-A53
    • AXI
    • NEON
    • Memory Management Unit (MMU)
    • Baremetal
    2085 views
    2 replies
    Latest over 1 year ago
    by Dylan Barrie
  • Answered

    Recommended ID width in AXI Protocol 0

    2201 views
    2 replies
    Latest over 1 year ago
    by Evan Lu
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone