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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Not Answered

    Can Cortex-M33 MCUs enable SAU and MPU_NS simultaneously? 0

    • mpu
    • Cortex-M
    • Cortex-M33
    • Armv8-M
    • SAU
    590 views
    0 replies
    Started 11 months ago
    by kiko
  • Answered

    Exception return issues with Cortex-M3 on STM32F103C8T6 0

    • Exception Handling
    • Interrupt Handling
    • stm32f103
    • Cortex-M3
    • STM32
    • Interrupt
    2294 views
    2 replies
    Latest 11 months ago
    by Nancen Li
  • Suggested Answer

    Socrates for SSE-315 subsystem 0

    1547 views
    2 replies
    Latest 11 months ago
    by Ian J Arm Employee Badge
  • Suggested Answer

    gic-600 interconnection through AXI-Stream interface 0

    • gic
    1604 views
    2 replies
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    What Causes Program Performance to Decline Despite an Increase in Cache Hit Rate? 0

    • Cortex-A76
    653 views
    0 replies
    Started 11 months ago
    by y say
  • Not Answered

    ASIC AES in ARM CPU, on data bus 0

    • Security
    547 views
    0 replies
    Started 11 months ago
    by Teddy Rahbe
  • Answered

    DVM operations in ARM ACE5 0

    3330 views
    7 replies
    Latest 11 months ago
    by Rohith Jonnabhatla
  • Suggested Answer

    AXI Write Interleaving 0

    • AMBA
    • AXI3
    • AXI
    • AXI4
    1835 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Invisible system cache 0

    2106 views
    4 replies
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Where I can get Implementation (iBEP) document for DSU 120 and Cortex-X925 +1

    1173 views
    1 reply
    Latest 11 months ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    How to downlaod pdf of an online document 0

    • Cortex-M7
    • web
    • Documentation
    1053 views
    1 reply
    Latest 11 months ago
    by frank_
  • Not Answered

    GPIO manipulation on A55 core of IMX93 with JTAG 0

    • JTAG
    • Cortex-A55
    • GPIO
    • uboot
    • secure
    1228 views
    0 replies
    Started 11 months ago
    by Adam Honeybell
  • Not Answered

    Relationship between ARM's shareability domain, cache maintenance and barrier 0

    • Cache coherency
    • Armv8-A
    • barrier
    • memory-model
    • Cache Architecture
    • Memory Management
    1589 views
    2 replies
    Latest 11 months ago
    by Joon Kang
  • Answered

    Return from MemManageFault +1

    • mpu
    • MemManageFault
    • Cortex-M4
    1783 views
    3 replies
    Latest 11 months ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Support for Huge Pages in SMMU 0

    • SMMUv3
    2261 views
    4 replies
    Latest 11 months ago
    by Jonathan Kang
  • Answered

    Memory Frequencies per Core 0

    • Memory Management Unit (MMU)
    • Cortex-A
    • x1
    1442 views
    2 replies
    Latest 11 months ago
    by FabianSchuetze
  • Answered

    Why might Loop Unrolling contribute to Lower Runtime When using two Cores (X1 or A76) but not with one Core? 0

    • Cortex-A76
    • Cortex-X
    1499 views
    2 replies
    Latest 11 months ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    ARM FM, CT M7 exception return, R7 register is not preserved 0

    706 views
    0 replies
    Started 11 months ago
    by Torbjörn Andersson
  • Answered

    Cache impacted memory region when MPU disabled. 0

    • Cortex-M7
    • Cortex-M
    1171 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
  • Answered

    What PMU Events describes Remote Reads 0

    • Performance Monitor Unit (PMU)
    1465 views
    2 replies
    Latest over 1 year ago
    by FabianSchuetze
<>
Topics being discussed in this forum
  • AArch64
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