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Cache impacted memory region when MPU disabled.

Richard Li

Hi,

I want to ask a question that if MPU is disabled in ARM CM-7 core, and D-Cache and I-Cache is enabled, what memory region will be cacheable?

If under this situation, all memory region could be cacheable, then what is the default cache policy?

BR

Richard

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    The memory attributes are determined from the default system address map or using an MPU. The default System Address Map is described in section B3.1 "The system address map" in the latest version of the Arm® v7-M Architecture Reference Manual, ARM DDI 0403E.e (ID021621), download from:

    https://developer.arm.com/documentation/ddi0403/latest/

    The "Cache" column in Table B3-1 "Armv7-M address map" indicates the area of the address map that are cacheable:

    0x00000000-0x1FFFFFFF WT

    0x20000000-0x3FFFFFFF WBWA

    0x60000000-0x7FFFFFFF WBWA

    0x80000000-0x9FFFFFF WT

    WT Write-Through.

    WBWA Write-Back, write allocate.

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    The memory attributes are determined from the default system address map or using an MPU. The default System Address Map is described in section B3.1 "The system address map" in the latest version of the Arm® v7-M Architecture Reference Manual, ARM DDI 0403E.e (ID021621), download from:

    https://developer.arm.com/documentation/ddi0403/latest/

    The "Cache" column in Table B3-1 "Armv7-M address map" indicates the area of the address map that are cacheable:

    0x00000000-0x1FFFFFFF WT

    0x20000000-0x3FFFFFFF WBWA

    0x60000000-0x7FFFFFFF WBWA

    0x80000000-0x9FFFFFF WT

    WT Write-Through.

    WBWA Write-Back, write allocate.

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