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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
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  • Answered

    In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not? +1

    • AMBA
    • AHB
    6823 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)? +1

    • Cortex-M7
    • Cache
    • Cortex-M
    4493 views
    4 replies
    Latest over 9 years ago
    by amanda_s
  • Answered

    AXI3 & AXI4 wrap burst length 0

    • AXI3
    • AXI4
    17291 views
    5 replies
    Latest over 9 years ago
    by Utkarsh Jain
  • Answered

    Embedded assembly function problem 0

    • Cortex-A9
    • NEON
    • Cortex-A
    5433 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Not Answered

    What does PMCEID0_EL0 determine for the the PMU? Performance monitor config 0

    • Cortex-A57
    • Cortex-A
    4855 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    ARMv7 architecture +1

    • Armv7-A
    5163 views
    2 replies
    Latest over 9 years ago
    by Myron Plichota
  • Answered

    Spin-lock implementation for Aarch64 -- how to enforce acquire semantics? 0

    • Armv7-A
    • AArch64
    • GNU
    18435 views
    2 replies
    Latest over 9 years ago
    by Olivier Delande
  • Answered

    Need to invalidate L1 cache after DMA on Cortex A9 +1

    • Cortex-A9
    • Cache
    • Cortex-A
    8700 views
    3 replies
    Latest over 9 years ago
    by Rohan
  • Answered

    Verilog bus functional models for AHB master simulation 0

    • AMBA
    • AHB Protocol
    • CMSDK
    • Cortex-M
    11099 views
    5 replies
    Latest over 9 years ago
    by serg
  • Not Answered

    My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag? 0

    • Cortex-M
    • Cortex-M4
    9769 views
    8 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    What is differene between cortex A, Cortex M and Cortex R series of ARM? 0

    • Cortex-R
    • Cortex-A
    • Cortex-M
    37989 views
    3 replies
    Latest over 9 years ago
    by tanveermalik
  • Answered

    How to configure Cortex-A57 PMU 0

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    • 64-bit
    9042 views
    5 replies
    Latest over 9 years ago
    by Michael
  • Answered

    Cannot access EL1 resources from EL3 or secure world on armv8. +1

    • Cortex-A53
    • Arm Trusted Firmware
    • Cortex-A
    • TrustZone
    9477 views
    4 replies
    Latest over 9 years ago
    by Tgn Yang
  • Answered

    AMBA AHB 0

    • AMBA
    • AHB
    8757 views
    6 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI3 data interleaving 0

    • AXI3
    7245 views
    2 replies
    Latest over 9 years ago
    by Utkarsh Jain
  • Not Answered

    Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32? 0

    • AArch64
    • Armv8-A
    • AArch32
    5429 views
    2 replies
    Latest over 9 years ago
    by 유영현
  • Answered

    CortexA8 L2 data loss 0

    • Cache
    • Cortex-A
    • Cortex-A8
    24535 views
    23 replies
    Latest over 9 years ago
    by Andreas Hauser
  • Answered

    I'm not seeing any flush-to-zero (FTZ) effects with NEON intrinsics on an ARM A9, any advice? +1

    • Armv8-A
    • NEON
    7189 views
    3 replies
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    TZC380: AXI ID and AID_WIDTH 0

    • TZC-380
    • TrustZone Controllers
    • AXI
    • Linux
    7126 views
    3 replies
    Latest over 9 years ago
    by Vincent Siles
  • Answered

    TZASC (TZC380) enabling sequence 0

    • Cortex-A9
    • Cortex-A
    7422 views
    4 replies
    Latest over 9 years ago
    by Vincent Siles
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone