Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Not Answered

    Pushing to the MSP stack instead when late arriving? 0

    • Armv7 Exception Model
    • R13 (SP Stack Pointer)
    • Armv7-M
    1154 views
    1 reply
    Latest over 2 years ago
    by ZacW
  • Answered

    AHB Bus Matrix Arbitration Delay 0

    • CMSDK
    2099 views
    2 replies
    Latest over 2 years ago
    by tjones95134
  • Not Answered

    Why branch to address with LSB=0 in non-secure state will trigger secure fault? 0

    • Control Flow Instructions
    • TrustZone
    1248 views
    0 replies
    Started over 2 years ago
    by Hiilda
  • Not Answered

    Problem with a Custom IP Slave AXI 0

    • FPGA Xilinx
    • AXI4
    2226 views
    3 replies
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    M23/TrustZone - failing to write SAU and SCB_NS 0

    • Cortex-M23
    • TrustZone
    2582 views
    5 replies
    Latest over 2 years ago
    by Hiilda
  • Not Answered

    Why function's address is loaded into VMA? 0

    • Cortex-M3
    • Memory
    1075 views
    0 replies
    Started over 2 years ago
    by nmmn1359
  • Answered

    Armv9 RME Cache access and GPC sequence order 0

    4039 views
    8 replies
    Latest over 2 years ago
    by josecm
  • Not Answered

    Can you tie off TLB if you're not using virtual memory? 0

    1148 views
    1 reply
    Latest over 2 years ago
    by 42Bastian Schick
  • Suggested Answer

    Is microSCU required for multi-cores to maintain coherency? +1

    1689 views
    3 replies
    Latest over 2 years ago
    by tjones95134
  • Answered

    Cortex-A15: How to access the Revision ID register, REVIDR 0

    • Cortex-A15
    1434 views
    2 replies
    Latest over 2 years ago
    by TimF
  • Suggested Answer

    Difference in coding format. 0

    • Base ISAs
    • SIMD ISAs
    1397 views
    2 replies
    Latest over 2 years ago
    by BobP
  • Answered

    SVC instruction execution inside the hard fault handler 0

    3248 views
    4 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    How to automatically detect Cortex M7 ALU overflow ?? 0

    • Interrupt Handling
    • Cortex-M7
    • Arm Compiler for Embedded FuSa
    1325 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    What is the unit of PMHF for R52 IP FMEDA 0

    • Cortex-R52
    836 views
    0 replies
    Started over 2 years ago
    by pengfu xie
  • Answered

    Equivalent of SSE4.2 needed for ARM support to CNDP Project 0

    3054 views
    6 replies
    Latest over 2 years ago
    by Annie
  • Not Answered

    ARMV8 arch64 how to handle bus error and interrupt occur together 0

    2086 views
    2 replies
    Latest over 2 years ago
    by Thomas Coding
  • Not Answered

    Cortex-M7 Failing to read PPB ROM table 0

    998 views
    0 replies
    Started over 2 years ago
    by Bert Hindle
  • Not Answered

    Debug Print Logs Display and Hardware Power Issue in KEIL uVision 5 (Cortex-M0) 0

    1385 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    SMMUv2 IRQS per Context Bank 0

    • SMMUv2
    791 views
    0 replies
    Started over 2 years ago
    by Jorge
  • Not Answered

    The pipeline of add with lsl >4 in Neoverse N1 0

    • Documentation
    • Neoverse N1
    949 views
    0 replies
    Started over 2 years ago
    by Juneyoung Lee
<>