Problem with a Custom IP Slave AXI


I have a problem with my custom IP. The idea its that i reply the behaviour of the BRAM CONTROLLER defined on the IP catalog of the Xilinx tool. 

The new behaviour its that i can define a different width, for example having a 128 bits on the AXI width an 64 bits on the side of the memory (BRAM).

My problem its when i am running all of the cores available on the KRIA KV260 (Zynq Ultrascale + family), i am see this warning 

Search on the internet they said that its related to a ATB register associate with the time out of the AXI, but i can understand what i am have to modify.

If someone have any idea to solve this problem pls help me! thx!

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