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Cortex-A8 - accessing banked registers from monitor mode

Jitesh Shah
Note: This was originally posted on 20th March 2012 at http://forums.arm.com

Hi Group,
I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

I know two ways I can do it:

1) Using the "mrs" instruction.
eg. mrs r0, sp_svc

However, my compiler (code sourcery) says:
Error: Banked registers are not available with this architecture. -- `mrs r0,sp_svc'

My architecture manual does say that banked registers are accessible via this method, so I suppose this is a compiler issue. Anyway.

2) Changing the mode to svc, reading sp and getting back to the monitor mode.

eg. cps MODE_SVC
mov r0, sp
cps MODE_MON

where MODE_SVC = 0x13 and MODE_MON = 0x16

But, as soon as I execute "cps MODE_SVC" in monitor mode, my CPU hangs. There is no more activity.

So my question is this: Is SVC mode not accessible from Monitor mode? If thats not the case, how can I access SVC version of the registers from Monitor mode?

Thanks,
Jitesh
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  • 0
    Note: This was originally posted on 21st March 2012 at http://forums.arm.com

    Basically, yes.  :-P

    As you guessed, Monitor mode is always in the Secure world.  Regardless of the value of the SCR.NS bit. 

    On entry to Monitor mode SCR.NS will reflect where you've just come from.  In your example SCR,NS=1, as you've come from the Normal world.  As Isogen said, the SCR.NS bit takes effect again immediately after you exit Monitor mode.  So when you do "CPS #Mode_Mon" you are dropping out of the Secure world into the Normal world.  Which means you;d have to trigger another exception to get back.

    Simple solution - clear the SCR.NS bit before you execute the CPS instruction.  You will need some code to check and remember what its state was as well.  I think there is an example from ARM which does this.
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  • 0
    Note: This was originally posted on 21st March 2012 at http://forums.arm.com

    Basically, yes.  :-P

    As you guessed, Monitor mode is always in the Secure world.  Regardless of the value of the SCR.NS bit. 

    On entry to Monitor mode SCR.NS will reflect where you've just come from.  In your example SCR,NS=1, as you've come from the Normal world.  As Isogen said, the SCR.NS bit takes effect again immediately after you exit Monitor mode.  So when you do "CPS #Mode_Mon" you are dropping out of the Secure world into the Normal world.  Which means you;d have to trigger another exception to get back.

    Simple solution - clear the SCR.NS bit before you execute the CPS instruction.  You will need some code to check and remember what its state was as well.  I think there is an example from ARM which does this.
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