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Cortex-A8 - accessing banked registers from monitor mode

Jitesh Shah
Note: This was originally posted on 20th March 2012 at http://forums.arm.com

Hi Group,
I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

I know two ways I can do it:

1) Using the "mrs" instruction.
eg. mrs r0, sp_svc

However, my compiler (code sourcery) says:
Error: Banked registers are not available with this architecture. -- `mrs r0,sp_svc'

My architecture manual does say that banked registers are accessible via this method, so I suppose this is a compiler issue. Anyway.

2) Changing the mode to svc, reading sp and getting back to the monitor mode.

eg. cps MODE_SVC
mov r0, sp
cps MODE_MON

where MODE_SVC = 0x13 and MODE_MON = 0x16

But, as soon as I execute "cps MODE_SVC" in monitor mode, my CPU hangs. There is no more activity.

So my question is this: Is SVC mode not accessible from Monitor mode? If thats not the case, how can I access SVC version of the registers from Monitor mode?

Thanks,
Jitesh
Parents
  • 0 Arm Employee Badge
    Note: This was originally posted on 21st March 2012 at http://forums.arm.com

    Also worth noting ..

    [color=#222222][size=2]Intention is to get the NS SVC mode SP
    [/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [size=2]There is no such thing as a "non-secure" SVC mode. The same physical registers are used for both secure and non-secure, so the SP value is the same irrespective of what the NS bit is, unless the monitor mode decides to modify it. So you can clear the NS bit, iterate save and restore all of the modes, and then drop into the secure world.[/size]
    [size=2]
    [/size]
Reply
  • 0 Arm Employee Badge
    Note: This was originally posted on 21st March 2012 at http://forums.arm.com

    Also worth noting ..

    [color=#222222][size=2]Intention is to get the NS SVC mode SP
    [/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [size=2]There is no such thing as a "non-secure" SVC mode. The same physical registers are used for both secure and non-secure, so the SP value is the same irrespective of what the NS bit is, unless the monitor mode decides to modify it. So you can clear the NS bit, iterate save and restore all of the modes, and then drop into the secure world.[/size]
    [size=2]
    [/size]
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