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Cortex-A8 - accessing banked registers from monitor mode

Jitesh Shah
Note: This was originally posted on 20th March 2012 at http://forums.arm.com

Hi Group,
I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

I know two ways I can do it:

1) Using the "mrs" instruction.
eg. mrs r0, sp_svc

However, my compiler (code sourcery) says:
Error: Banked registers are not available with this architecture. -- `mrs r0,sp_svc'

My architecture manual does say that banked registers are accessible via this method, so I suppose this is a compiler issue. Anyway.

2) Changing the mode to svc, reading sp and getting back to the monitor mode.

eg. cps MODE_SVC
mov r0, sp
cps MODE_MON

where MODE_SVC = 0x13 and MODE_MON = 0x16

But, as soon as I execute "cps MODE_SVC" in monitor mode, my CPU hangs. There is no more activity.

So my question is this: Is SVC mode not accessible from Monitor mode? If thats not the case, how can I access SVC version of the registers from Monitor mode?

Thanks,
Jitesh
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  • 0
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Have you initialized the SVC mode, and is the NS-bit configured as secure before you call cps?

    If you are in monitor mode when you do the "cps MODE_SVC" are you are effectively switching into SVC mode, using it's banked registers, so if you haven't initialized them you are probably going to have problems.

    My best guess is that you've got the NS-bit set to 1 (i.e. non-secure) and you switch modes, which drops the core in to non-secure SVC mode, because the NS-bit takes effect as soon as you drop out of monitor mode. It is quite possible that the PC you are using doesn't exist in the non-secure world, so it faults, but  the non-secure exception table is also not set up, so that faults. Infinite loop of faults = hung CPU.

    Iso
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  • 0
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Have you initialized the SVC mode, and is the NS-bit configured as secure before you call cps?

    If you are in monitor mode when you do the "cps MODE_SVC" are you are effectively switching into SVC mode, using it's banked registers, so if you haven't initialized them you are probably going to have problems.

    My best guess is that you've got the NS-bit set to 1 (i.e. non-secure) and you switch modes, which drops the core in to non-secure SVC mode, because the NS-bit takes effect as soon as you drop out of monitor mode. It is quite possible that the PC you are using doesn't exist in the non-secure world, so it faults, but  the non-secure exception table is also not set up, so that faults. Infinite loop of faults = hung CPU.

    Iso
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