In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by "no additional state saving"?
Does it mean that the Stack saved for LP is going to work for HP as well? If yes, how the HP will get to know that where it has to return after servicing the interrupt because Link Register that is stored for LP will cause the switching from Handler Mode to Thread mode but we actually want the switching from Handler mode to Handler mode and for this, we need to have new LR specifically saved when HP is about to get executed.
Thanks
Vartika
So, before entering HP, in LR, does EXC_RETURN value 0xfffffff1 ( returning to handler mode) is loaded so that HP after executing handler returns back to LP?
Both HP IRQ handler and LP IRQ handler will see EXC_RETURN indicating return to thread (0xFFFFFFF9).
It is return to thread because there has been just one level of stacking carried out. In other word, tail-chaining is not the same as nested interrupt as the second IRQ handler hasn't started executing when the first one is started.
regards,
Joseph