In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by "no additional state saving"?
Does it mean that the Stack saved for LP is going to work for HP as well? If yes, how the HP will get to know that where it has to return after servicing the interrupt because Link Register that is stored for LP will cause the switching from Handler Mode to Thread mode but we actually want the switching from Handler mode to Handler mode and for this, we need to have new LR specifically saved when HP is about to get executed.
Thanks
Vartika
The registers saves by the LP IRQ are state information for the interrupted thread, which is exactly the same for the LP IRQ and the HP IRQ, including the LR being pushed into the stack which is the return address of the interrupted code (the stacked LR is not EXC_RETURN).
In this case, the stacking sequence for saving interrupted thread don't have to be changed (carry on as usual, or if it is already completed, then there is no extra register stacking). In this scenario, only the vector fetch might need to be repeated if the LP IRQ vector has already been fetched, as the processor need to fetch the vector for the highest priority IRQ.
At the end of the handler for the HP IRQ ,the processor see the EXC_RETURN (was in LR) being loaded into PC. However, it is aware that there is a pending interrupt to be serviced (the NVIC is integrated with the processor so this information is available). So instead of starting unstacking, it tail chain into the LP IRQ handler (a vector fetch is needed at this stage for the LP IRQ).
Please note that if the EXC_RETURN code (e.g. SPSEL) has been modified by the first IRQ handler (HP), at the exception entry of the second IRQ handler (LP) the value of the EXC_RETURN (in LR) would take the modified value.
After the LP IRQ handler is completed, the return mechanism returns the program execution to the interrupt thread.
regards,
Joseph
So, before entering HP, in LR, does EXC_RETURN value 0xfffffff1 ( returning to handler mode) is loaded so that HP after executing handler returns back to LP?
Both HP IRQ handler and LP IRQ handler will see EXC_RETURN indicating return to thread (0xFFFFFFF9).
It is return to thread because there has been just one level of stacking carried out. In other word, tail-chaining is not the same as nested interrupt as the second IRQ handler hasn't started executing when the first one is started.