The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h?
The full description is in the ARMv7-M manual. This is the "architecture" manual, which describes what is possible with a Cortex-M. The other is the discrete implementation of the architecture, here a Cortex-M7. And then there are the final SoC. Each step allows to remove things. Like here: The architecture defines up to 8 of these, while the CM7 only has one.Or take the NVIC. It defines up to 240 interrupts sources, but not every SoC uses so many.
HTH