The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h?
The Cortex-M7 manual only has one ITM_TER register correct. However, while the register is in the table summary, further details of the register are not in the manual. The image below is the only mention of the ITM_TER register in the manual. Where can a full description of the register be found?
Secondly, the reference manual names the stimulus ports ITM_STIM but core_cm7.h names the ports PORT[]. Is there a naming mismatch between the manual and core_m7.h?
The Cortex-M7 manual names the stimulus ports ITM_STIM
core_m7.h names the stimulus ports PORT[]
The full description is in the ARMv7-M manual. This is the "architecture" manual, which describes what is possible with a Cortex-M. The other is the discrete implementation of the architecture, here a Cortex-M7. And then there are the final SoC. Each step allows to remove things. Like here: The architecture defines up to 8 of these, while the CM7 only has one.Or take the NVIC. It defines up to 240 interrupts sources, but not every SoC uses so many.
HTH