What is different between write back with write allocate and write with non write allocate on Cortex-M4.
Cache policies:
Allocation policy
A read allocate policy allocates a cache line only on a read.
A write allocate policy allocates a cache line for either a read or write which misses in the cache (and so might more accurately be called a read-write cache allocate policy). For both memory reads which miss in the cache and memory writes which miss in the cache, a cache linefill is performed. This is typically used in combination with a write-back write policy on current ARM processors
Write policy
Write-through. With this policy writes are performed to both the cache and main memory.
Write-back. In this case, writes are performed only to the cache, and not to main memory.(When a write happens which updates the cache, but not main memory, the dirty bit is set. If the cache later evicts a cache line whose dirty bit is set (a dirty line), it writes the line out to main memory.)
Conclusion: write-back with write allocate - write to cache and not to main memory, later when cache eviction happens - main memory will be updated with data from evicted cache line.
write-through with write allocate - write to both the cache and main memory (performance of processor is degraded because of wasting time to wait write operations)
write with non write allocate - write directly to main memory
Sorry, there is a typo. My question is the difference between write back + write allocate and write back + write no allocate on Cortex-M4.
For example, if the address space is cache-able with write back and write no allocate attribute, when write to this space happen and it is not cache hint yet, on CM4, does cache line allocate happen? or just push data to physical device?
I see such description in CA7 TRM:
“All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cache allocate hint, though this can dynamically switch to no write-allocate, if more than three full cache lines are written in succession.”
But i don't find similar description on CA8, CA53 and CM4 TRM, so have some confusions.