What is different between write back with write allocate and write with non write allocate on Cortex-M4.
Sorry, there is a typo. My question is the difference between write back + write allocate and write back + write no allocate on Cortex-M4.
For example, if the address space is cache-able with write back and write no allocate attribute, when write to this space happen and it is not cache hint yet, on CM4, does cache line allocate happen? or just push data to physical device?
I see such description in CA7 TRM:
“All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cache allocate hint, though this can dynamically switch to no write-allocate, if more than three full cache lines are written in succession.”
But i don't find similar description on CA8, CA53 and CM4 TRM, so have some confusions.
I konw your meaning, your precondition is write-miss policy in write back and CM4.
first, both write-through and write-back policy can use write allocate and write no allocate when write-miss.
second, write-back policy use write allocate usually.
so i think it should be the write allocate even though it has write no allocate attribute, maybe it has a parameter that can be configured or has the priority.
you can look up it in ARM architecture Manual. I will tell you if I find out the correct answer.