Hello All,I had a couple of clarifications w.r.t the ARMv8 docs and Virtual IRQ/FIQ exceptions in conjunction with HCR.{IMO,FMO} bits and interrupt routing.A) Does this mechanism require a GIC or can it function without one?B) I am experimenting with a hypervisor and a custom guest and here is a rundown of what I am wanting to accomplish: 1 HYP mode: set HCR.IMO=1 and start gues
2. guest SVC mode: setup VBAR and IRQ/FIQ vectors and enable timer/interrupts
3. HYP mode: IRQ handler: gets control and sets HCR.VI=1
4. guest IRQ mode: IRQ handler gets control and calls into HYP mode via hypercall-0
5. HYP mode: hypercall handler 0: set HCR.VI=0 and resume guest1, 2 and 3 above work. However, for some reason 4 is not triggered but I keep looping at 3 on the same guest PC in SVC mode just afterinterrupts are enabled.My understanding is that setting the HCR.VI should trigger the guest IRQ handler, but it is not doing so in my case.Any insights?
I should add:
I have interrupts disabled in HYP mode. i.e. CPSR.{A,I.F}=1 in HYP mode.
Are you clearing the IRQ source before returning to svc mode?
If the irq line is still asserted you'd see this behaviour.
Ahh, I am currently not clearing the IRQ source, so that is probably the cause of the loop. Thanks Peter.
Another clarification: If I clear the IRQ source and set HCR.VI=1 in step-3, can the HYP mode IRQ handler re-trigger due to another physical interupt when in step-4 (where guest IRQ handler in svc mode executes )? In other words, does setting HCR.VI mask all the physical interrupts until such time the guest IRQ handler executes hypercall-0 to clear HCR.VI ?
Happy to help.
When HCR.IMO=1 and executing at PL1 (svc, irq etc modes) physical irqs are unmaskable and will always bounce you to hyp mode.
In this config the cpsr.irq mask @pl1 only affects virtual irqs.