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Control access to L2 cache

Hi,

I want to use a dual core with shared L2 cache. On Core0 I want to run Linux and on Core1 I want to run Bare - Metal. Is it possible to control the L2 cache access in case both Cores want to access the L2 cache at the same time. In that case I want Core1 get prior access...

Thanks

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0 christoph8446 over 7 years ago in reply to 42Bastian Schick

Another question, the SCU is connected via two AXI master and two AXI slave ports to the L2 cache. Can both cores have access to the L2 cache simultaneous and in case not why I have two master ports?
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0 christoph8446 over 7 years ago in reply to 42Bastian Schick

Another question, the SCU is connected via two AXI master and two AXI slave ports to the L2 cache. Can both cores have access to the L2 cache simultaneous and in case not why I have two master ports?
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0 christoph8446 over 7 years ago in reply to christoph8446

OK

The Cortex-A9 L2 interface consists of two 64-bit wide AXI bus masters:

•M0 is the data side bus

•M1 is the instruction side bus and has no write channels.
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