Control access to L2 cache

I think it depends on the SoC you use and the cache.
On L2C310 cache for example you can lock on master so there is one half of the cache for core0 and one for core1 since it has two master and slave ports, I would expect minimal impact. But if you need to have determinism down to this level you should consider to disable cache in the core1 (at least 2nd level).
But I doubt that you can reach determinism on an ARMv8-A CPU.

I think it depends on the SoC you use and the cache.
On L2C310 cache for example you can lock on master so there is one half of the cache for core0 and one for core1 since it has two master and slave ports, I would expect minimal impact. But if you need to have determinism down to this level you should consider to disable cache in the core1 (at least 2nd level).
But I doubt that you can reach determinism on an ARMv8-A CPU.

Another question, the SCU is connected via two AXI master and two AXI slave ports to the L2 cache. Can both cores have access to the L2 cache simultaneous and in case not why I have two master ports?

OK