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Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?

Hi Fellows,

I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR  SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction etc. after it? If yes, what are the performance overheads if any? The reference manual does say the following:

"Changing PSTATE.SPSel to use EL0 synchronizes any updates to SP_EL0 that have been written by an MSR to SP_EL0, without the need for additional synchronization."

But I am not sure it concerns my question. Thanks.

Best Regards,

Mughees

Parents
  • Hi,

    The line you quote deals with synchronization between writes to SP_EL0 and making it active, so solves half the problem.  It means that:

    MSR SP_EL0, x0

    MSR SPSel, #0

    Doesn't need any extra barriers.

    The other interesting part in the spec is:

    "Writes to the PSTATE fields have side-effects on various aspects of the PE operation. All of these side-effects are
    guaranteed:
    • Not to be visible to earlier instructions in the execution stream.
    • To be visible to later instructions in the execution stream."

    Which deals with when you can guarantee which SP is used.:

    MSR SPSel, #0

    STP x3, x4, [sp] // SP is now SP_EL0

     

    Pete.

Reply
  • Hi,

    The line you quote deals with synchronization between writes to SP_EL0 and making it active, so solves half the problem.  It means that:

    MSR SP_EL0, x0

    MSR SPSel, #0

    Doesn't need any extra barriers.

    The other interesting part in the spec is:

    "Writes to the PSTATE fields have side-effects on various aspects of the PE operation. All of these side-effects are
    guaranteed:
    • Not to be visible to earlier instructions in the execution stream.
    • To be visible to later instructions in the execution stream."

    Which deals with when you can guarantee which SP is used.:

    MSR SPSel, #0

    STP x3, x4, [sp] // SP is now SP_EL0

     

    Pete.

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