Hi experts,
ldp x1, x2, [x0], #16
x0 = 0x100004. It is a RAM address, and it is valid and available.
This instruction will trigger an exception. why?
If x0 = 0x100000 or x0 = 0x100008, it can work well.
Thanks,
Jorney
The address isn't 8-byte aligned - but I would have thought it should still have worked.
Check that alignment check is disabled, if the A bit in SCTLR_EL1 (or whatever level) is set then alignment checks are enabled.
In addition ...
If this is part of boot code or driver code which is talking to device or strongly ordered memory types, note that unaligned accesses are not supported for these memory types; only normal memory allows unaligned accesses. Therefore check your page table setup code to ensure that your RAM region is marked as "normal" memory type.
Also note that the memory system (even normal RAM) behaves like strongly ordered memory when the MMU is disabled, so boot code which runs before the MMU is turned on (or shutdown code which runs after it is turned off) must be written to only make aligned accesses.
Cheers, Pete
Hi Daith,
Thanks for your replay.
SCTLR_EL1.A , SCTLR_EL2.A, and SCTLR_EL3.A are disabled.
The code runs on EL3 in the DRAM.
Hi Harris,
Thank you for reply.
This code runs before the MMU is enabled.
According to your suggestion, I move it after the MMU is enabled, It runs well.
Thanks again,
Where can I find the specification about this issue in ARMv8 Architecture Reference Manual ?
In the current document issue (A.k).
Section B 2.2 describes the two memory types in ARMv8 ("Normal" and "Device"); the ARMv7 "Strongly Ordered" no longer exists as a separate memory type - that has effectively been merged as sub-type of the "Device" memory type in ARMv8 (See B 2.8.2).
Section B 2.4.2 describes the limitations on unaligned access for data accesses. Specifically:
"An unaligned access to any type of Device memory causes an Alignment fault."
The behaviour when translation is disabled is defined in section D4.2.8. Specifically:
"All other accesses: Data access: The stage 1 translation assigns the Device-nGnRnE memory type."
"All other accesses:
Data access:
The stage 1 translation assigns the Device-nGnRnE memory type."
Cheers,Pete
I've never felt the need to treat integers or longs as unaligned - but I can see this tripping up some things like a memory move if one just copies over the usual algorithm to early in the boot process.