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when and where will the LDP instruction trigger an exception ?

Hi experts,

     ldp x1, x2, [x0], #16

     x0 = 0x100004. It is a RAM address, and it is valid and available.

     This instruction will trigger an exception. why?

     If x0 = 0x100000 or x0 = 0x100008, it can work well.

    

     Thanks,

     Jorney

Parents
  • Hi Harris,

         Thank you for reply.

         This code runs before the MMU is enabled.

         According to your suggestion, I move it after the MMU is enabled, It runs well.

         Thanks again,

        

        Where can I find the specification about this issue in ARMv8 Architecture Reference Manual ?

         Jorney

Reply
  • Hi Harris,

         Thank you for reply.

         This code runs before the MMU is enabled.

         According to your suggestion, I move it after the MMU is enabled, It runs well.

         Thanks again,

        

        Where can I find the specification about this issue in ARMv8 Architecture Reference Manual ?

         Jorney

Children
  • Where can I find the specification about this issue in ARMv8 Architecture Reference Manual ?

    In the current document issue (A.k).

    Section B 2.2 describes the two memory types in ARMv8 ("Normal" and "Device"); the ARMv7 "Strongly Ordered" no longer exists as a separate memory type - that has effectively been merged as sub-type of the "Device" memory type in ARMv8 (See B 2.8.2).

    Section B 2.4.2 describes the limitations on unaligned access for data accesses. Specifically:

    "An unaligned access to any type of Device memory causes an Alignment fault."

    The behaviour when translation is disabled is defined in section D4.2.8. Specifically:

    "All other accesses:

        Data access:

            The stage 1 translation assigns the Device-nGnRnE memory type."

    Cheers,
    Pete

  • I've never felt the need to treat integers or longs as unaligned - but I can see this tripping up some things like a memory move if one just copies over the usual algorithm to early in the boot process.