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Can't understand the difference between armv7e-m and armv7e-m-pic?

Hello people. I'm trying to do libgcc extraction for hard FPU's for k70 tower board. However, when I look at the libgcc library for arm targets, I find armv7-m, armv7e-m and armv7e-m-pic. I'm able to deduce from the armv7-m reference manual that the difference between armv7-m and armv7e-m is of the DSP chip i.e. armv7e-m will have a DSP chip. As the k70 has a DSP chip, therefore I'm able to conclude that I have the armv7e-m architecture. However, I'm unable to figure out the difference between armv7e-m and armv7e-m-pic? There is no reference about it in the armv7-m reference manual. Can someone help me out here?

Thanks,
Bilal

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  • Hi Bilal,


    I think that 'pic' means the position independent code.
    In the pic mode, all load and store instruction would be PC relative or a certain base register relative.
    For example of GCC, GCC generates r3 relative codes for load or store in the pic mode.
    1) source

    volatile int a,b,c;
    int main()
    {
     c = a+b;
    }
    

    2) option: -march=armv7e-m -mthumb

    main:
            ldr    r2, .L2
            ldr    r3, .L2+4
            ldr    r1, [r2]
            ldr    r3, [r3]
            ldr    r2, .L2+8
            add    r3, r3, r1
            str    r3, [r2]
            movs    r0, #0
            bx      lr
    .L3:
            .align  2
    .L2:
            .word  a
            .word  b
            .word  c
    

    3) option: -march=armv7e-m -fpic -mthumb

    main:
            ldr    r3, .L2
            ldr    r1, .L2+4
            ldr    r2, .L2+8
    .LPIC0:
            add    r3, pc
            ldr    r0, [r3, r1]
            ldr    r2, [r3, r2]
            ldr    r1, .L2+12
            ldr    r0, [r0]
            ldr    r2, [r2]
            ldr    r1, [r3, r1]
            adds    r3, r0, r2
            str    r3, [r1]
            movs    r0, #0
            bx      lr
    .L3:
            .align  2
    .L2:
            .word  _GLOBAL_OFFSET_TABLE_-(.LPIC0+4)
            .word  a(GOT)
            .word  b(GOT)
            .word  c(GOT)
    

    As the results, armv7e-m and armv7e-m-pic would be indentical other than the addressing mode.

    Best Regards,
    Yasuhiko Koumoto.

Reply
  • Hi Bilal,


    I think that 'pic' means the position independent code.
    In the pic mode, all load and store instruction would be PC relative or a certain base register relative.
    For example of GCC, GCC generates r3 relative codes for load or store in the pic mode.
    1) source

    volatile int a,b,c;
    int main()
    {
     c = a+b;
    }
    

    2) option: -march=armv7e-m -mthumb

    main:
            ldr    r2, .L2
            ldr    r3, .L2+4
            ldr    r1, [r2]
            ldr    r3, [r3]
            ldr    r2, .L2+8
            add    r3, r3, r1
            str    r3, [r2]
            movs    r0, #0
            bx      lr
    .L3:
            .align  2
    .L2:
            .word  a
            .word  b
            .word  c
    

    3) option: -march=armv7e-m -fpic -mthumb

    main:
            ldr    r3, .L2
            ldr    r1, .L2+4
            ldr    r2, .L2+8
    .LPIC0:
            add    r3, pc
            ldr    r0, [r3, r1]
            ldr    r2, [r3, r2]
            ldr    r1, .L2+12
            ldr    r0, [r0]
            ldr    r2, [r2]
            ldr    r1, [r3, r1]
            adds    r3, r0, r2
            str    r3, [r1]
            movs    r0, #0
            bx      lr
    .L3:
            .align  2
    .L2:
            .word  _GLOBAL_OFFSET_TABLE_-(.LPIC0+4)
            .word  a(GOT)
            .word  b(GOT)
            .word  c(GOT)
    

    As the results, armv7e-m and armv7e-m-pic would be indentical other than the addressing mode.

    Best Regards,
    Yasuhiko Koumoto.

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