the arm7tdmi data sheet states that the PLL multiplier factor is register APMC_CGMR(13:8) but the examples I have seen set this to (000011) which when +1 added to this value sets the PLL to X4 (16MHz x 4 = 64MHz, which is greater then 32MHz)
Hi rlittaz,
What specific part are you using, is it Atmel's AT91M55800A? If the MUL field in APMC_CGMR is 000011, Master Clock (MCK) will not exceed the 33 MHz limit if the PRES field is in the range 001 (÷2) to 110 (÷64), otherwise the crystal must be of lower frequency (8 MHz).
Regards,
Goodwin
I was incorrect – the MUL field of register APMC_CGMR is set to 0b000001. The crystal on the hardware is 16MHz, therefore, the PLL will be set to (MUL+1) x 16MHz = 2x16MHz = 32MHz which is the correct MAX PLL frequency . Note: PRES = 0b000, so there is no prescaler selected.
Thanks for the assistance.
Richard Litt
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That cleared the issue. While division can keep Master Clock (MCK) below 33 MHz, the PLL, CSS mux, and Prescaler themselves might not work above that limit.