the arm7tdmi data sheet states that the PLL multiplier factor is register APMC_CGMR(13:8) but the examples I have seen set this to (000011) which when +1 added to this value sets the PLL to X4 (16MHz x 4 = 64MHz, which is greater then 32MHz)
That cleared the issue. While division can keep Master Clock (MCK) below 33 MHz, the PLL, CSS mux, and Prescaler themselves might not work above that limit.