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v7M debug architecture questions

cray

Dear sirs,

Regarding v7m debug architecture, I have some questions after reading the v7m architecture document.

Q1: There is no mechanism to send instruction to the core for execution in debug state, is that true?

I guess the architecture uses  debug return address value register to start debug instruction exectution, is that right?

cray

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    Yes, that is correct. ARMv7-M has a different style of architecture where the processor is completely halted in Debug state. The DCRDR and DCRSR are used to access the processor registers: everything else is memory mapped and can be directly accessed via the DAP. Contrast this with the "A" profile processors which have coprocessors and multiple exception levels with Banked registers, and you can see why these architectures take different approaches.

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    Yes, that is correct. ARMv7-M has a different style of architecture where the processor is completely halted in Debug state. The DCRDR and DCRSR are used to access the processor registers: everything else is memory mapped and can be directly accessed via the DAP. Contrast this with the "A" profile processors which have coprocessors and multiple exception levels with Banked registers, and you can see why these architectures take different approaches.

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