can anyone tell me the difference between pipelined bus and depipelined bus?and i have uploaded two screen shot of both so what does that arrow from mclk to a[31:0] indicates?

thank you for such wonderful  answer,

you said that  the arrow in each diagram shows the MCLK edge that was used by the ARM7TDMI processor to drive out the A[31:0] value, MCLK rising when APE is high (the pipelined timing), and MCLK falling when APE is low (the "de-pipelined" timing).

but in both diagram A[31:0] is being latched after edges(i.e on either high level or low level of clock),so can you tell me why?

and in articles of arm7, it is said that in arm7tdmi, both negative edge and positive edge of MCLK are  used so how it is used?

thank you for such wonderful  answer,

you said that  the arrow in each diagram shows the MCLK edge that was used by the ARM7TDMI processor to drive out the A[31:0] value, MCLK rising when APE is high (the pipelined timing), and MCLK falling when APE is low (the "de-pipelined" timing).

but in both diagram A[31:0] is being latched after edges(i.e on either high level or low level of clock),so can you tell me why?

and in articles of arm7, it is said that in arm7tdmi, both negative edge and positive edge of MCLK are  used so how it is used?

Inside the ARM7TDMI it will be generating its internal address value on the MCLK rising edges, so what you see in the "pipelined addresses" diagram.

However if you want the "depipelined addresses" timing, APE will select between the internal address timing when APE=1, and a version of the address either registered on MCLK rising edges or latched (open on MCLK low) when APE=0.

The "depipelined" timing would be offered to simplify interfacing with static RAM type slaves where address and data need to be valid at the same time, but the native "pipelined" timing should result in fewer wait states in higher clock speed systems because the address is known before when the slave needs to perform a data transfer. So APE allows you to select the timing best suited to your design.

As you can see in the "pipelined" timing diagram, nMREQ and SEQ are driven following MCLK falling edges, then ADDR is driven following MCLK rising edges, and the data transfer completes on MCLK falling edges, so both edges of MCLK need to be used by the system (your slaves need to know which clock edge to use to sample each input, and when to drive outputs so that they will be valid when the ARM7TDMI is sampling them). Not sure if that answers your "how is it used" question.

Using both edges of MCLK is not readily supported by synthesis tools and cell libraries, and can lead to critical timing paths, so more modern bus protocols only use rising edges of the clock (AHB, AXI and so on).

JD