Dear All,
I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU).
Till now i was able to find quite limited references that were not much helpful.
If any of you know anything related to execution in "Second execution unit of ARM cortex A9" or any related references, please let me know!!
Also it is possible to discuss further here in the forum directly. Looking forward to your input.
Thanks & regards.
You are basically correct. Yes, there are two ALU back-end pipelines, following a common front-end. The front end pipeline consists of 6 stages, handling pre-fetch (three stages), instruction queue, decode and register rename. There are a total of four back-end pipelines. Two are ALU execution pipes, both capable of handling any ALU instruction. One is capable of also handling MAC instructions. The remaining two are a Load/store pipeline and a separate pipeline for the NEON/Float compute engine.
That much you can learn by attending one our excellent training courses! We don't generally disclose any more detailed information than that.
May I ask why you are interested in the pipeline structure? Are you trying to solve a particular optimization problem?
Chris
Thank you so much sir...that was quite helpful.
Big fan of your videos on youtube!!
I am just a student who is using Zynq 7000 SoC platform for embedded systems studies.
I was using PMU to analyze the kernel and user activity over linux running on Microzed development board!!
You're most welcome. I'm glad you found that helpful. The Zynq is an excellent platform for system exploration.
Always nice to hear that the videos are useful!
Best wishes