can we delay read and write transactions(axi4) by providing delay in register slice?

Hello Preet Kaur Walia,

I shall mask arready such that handshaking is not possible.

Yes, you shall.

Also by making outstanding one you mean that the master cannot send second address before first data from first

read  transaction is read back?

Yes, it does.

Best regards,
Yasuhiko Koumoto.

Sir

I am working on the read and write as per your suggestions.

Regards

Preet Kaur Walia

Sir

The read is working fine but write is not.

As you mentioned the write will work similarly but it does not.

If I do a single write it is getting written on memory without delay(I am assuming the first data mask is not working for it)

Burst is not working.

Regards

Preet Kaur Walia

Sir

The write is still not working.

i have a doubt. According to the timing you have assumed it states that during a write transaction the wvalid will be asserted after awready.

But in the manual ambaaxi it has been quoted that "

It is important that during a write transaction, a master must not wait for AWREADY

to be asserted before driving WVALID. This could cause a deadlock condition if the

slave is conversely waiting for WVALID before asserting AWREADY.

"

Then the logic would fade.

Regards

Preet Kaur Walia

Hello Preet Kaur Walia.

I am sorry. I forget the current First_WDATA_Mask would be too late to stop the first data cycle.

I think that if the reset value of First_WDATA_Mask was '1' and it would become '1' at every writing done (BVALID&BREADY), it might go well.

always@(posedge CLK) begin 
if(~ARESETN) 
  FIRST_WDATA_MASK <= 1; 
else if(BREADY&BVALID) 
  FIRST_WDATA_MASK <= 1; 
else if(WADDR_DONE&WVALID&WREADY) 
  FIRST_WDATA_MASK <= 0; 
end 

Best regards,

Yasuhiko Koumoto.

Sir

I have done the following change to the code and it seems to work.

As we donot know that awready will be high before or after wvalid. Therefore there is possibility that first data mask will remain 1 as this condirion may not get true

1. always@(posedge CLK) begin  
2. if(~ARESETN)  
3.   FIRST_WDATA_MASK <= 0;  
4. else if(AWVALID&masked_AWREADY)  
5.   FIRST_WDATA_MASK <= 1;  
6. else if(WADDR_DONE&WVALID&WREADY)   //this condition might not be true
7.   FIRST_WDATA_MASK <= 0;  
8. end  

the changed code

1. always@(posedge CLK) begin  
2. if(~ARESETN)  
3.   FIRST_WDATA_MASK <= 0;  
4. else if(AWVALID & masked_AWREADY)  
5.   FIRST_WDATA_MASK <= 1;  
6. else if(WADDR_DONE & WREADY)   //change
7.   FIRST_WDATA_MASK <= 0;  
8. end  

regards

Preet Kaur Walia

Sir

None of the solutions seem to work and I am not able to figure out the reason.

Regards

Preet Kaur Walia

Hello Preet Kaur Walia,

it's sad news.
By the way, you said that if the following logic was used, it went well.

always@(posedge CLK) begin  
if(~ARESETN)  
  FIRST_WDATA_MASK <= 0;  
else if(AWVALID & masked_AWREADY)  
  FIRST_WDATA_MASK <= 1;  
else if(WADDR_DONE & WREADY)  //change
  FIRST_WDATA_MASK <= 0;  
end 

If it is correct, I guess that your master would not assert WVALID until getting WREADY from the slave. But it would violate the AXI specs.
Can you confirm it?
If you can confirm it, I should compromise the description above.
To the contrary, if your slave would not assert WREADY until getting WVALID from the master, "else if(WADDR_DONE & WREADY)" would be replaced for "else if(WADDR_DONE & WVALID)".

By the way, I have found something was wrong.
"else if(AWVALID&masked_AWREADY)" would be strange (also in the read case).
I'm sorry but I think masked_AWREADY should be AWREADY.

I am afraind WADDR_DONE would not become "1" with the previous description.
Therefore, the logics would be the following.

always@(posedge CLK) begin  
if(~ARESETN)  
  WADDR_DONE <= 0;  
else if(AWVALID&AWREADY)  
  WADDR_DONE <= 1;  
else if(BVALID&BREADY)  
  WADDR_DONE <= 0;  
end  
always@(posedge CLK) begin  
if(~ARESETN)  
  FIRST_WDATA_MASK <= 1;  
else if(AWVALID&AWREADY)  
  FIRST_WDATA_MASK <= 1;  
else if(WADDR_DONE&(wcounter==4'hf))  
  FIRST_WDATA_MASK <= 0;  
end  
always@(posedge CLK) begin  
if(~ARESETN)  
  wcounter <= 4'h0;  
else if(WADDR_DONE&masked_WVALID&masked_WREADY)  
  wcounter <= 4'hf;  
else if(wcounter!=4'h0)  
  wcoubter <= wcounter -1 ;  
end  
assign mask_pre = (wcouner != 4'h0);  
assign WREADY_mask = FIRST_WDATA_MASK | mask_pre;  // CHANGE!  
assign WVALID_mask = mask_pre;                    // CHANGE!  
assign masked_WVALID = WVALID & ~WVALID_mask; // RVALID for master  
assign masked_WREADY = WREADY & ~WREADY_mask;  // RREADY for slave  
assign masked_AWREADY = ~WADDR_DONE & AWREADY; // this make outstanding 1 

How about them?
I'm sorry for you inconvenience.

Best regards,

Yasuhiko Koumoto.

Sir

The condition

always@(posedge CLK) begin   

     if(~ARESETN)   

           FIRST_WDATA_MASK <= 1;    // new change 

     else if(AWVALID & masked_AWREADY)   

            FIRST_WDATA_MASK <= 1;   

     else if(WADDR_DONE & WREADY) 

           FIRST_WDATA_MASK <= 0;   

end  

should work fine considering that wvalid and wready need not be high together. Therefore, it might be possible that wvalid has gone high for a clock cycle and aftersometime wready goes high. Data mask should go low after that. Therefore it would not deviate from the AXI specification.

Hello,

if the releasing the FIRST_WDATA_MASK only by WREADY made your system working fine, it's a good news.
I think the characteristic of  "wvalid has gone high for a clock cycle and aftersometime wready goes high" would be strange because the assertions (i.e. go to High) WVALID and WREADY should be independent.
If the master makes WVALID high before the  slave makes WREADY high, the FIRST_WDATA_MASK logic cannot stop the data cycle.
The logic will only go well if the WVAID of the master will go high after the slave would make WREADY high.
Anyway, there would be the timing WVALID and WREADY will be High at the same and I wonder why "WADDR_DONE & WVALID & WREADY" would be wrong for de-asserting FIRST_WDATA_MASK.
The only possibility would be WADDR_DONE was '0' at the timing when "WVALID & WREADY" was '1'. These are the cases <1> and <2> of my previous post.
I will propose the new condition for releasing FIRST_WDATA_MASK.
Could you please try it?

always@(posedge CLK) begin    
     if(~ARESETN)    
           FIRST_WDATA_MASK <= 1;    // new change  
     else if(AWVALID & AWREADY)    
            FIRST_WDATA_MASK <= ~(WVALID & WREADY);    
     else if(WADDR_DONE & WVALID & WREADY)  
           FIRST_WDATA_MASK <= 0;    
end   

Best regards,
Yauhiko Koumoto.

Sir

I am working on it. Also I had a query that in the write case ,

According to me the following scenario should be followed:

We should  mask wvalid as we need to stop the wvalid from the CPU from going to the slave otherwise, it will do the write transaction as and when wvalid is high.Slave will then send wready (telling the CPU it is ready to accept more data).

Whereas we are working on the contrary. As it can be seen from the first data mask situation, wready is being masked and wvalid is being sent to the slave. Therefore, there is a possibilty that slave has already written the data to memory before we are providing the delay. (in the first data mask situation we are only masking the wready)

1. assign WREADY_mask = FIRST_WDATA_MASK | mask_pre;  // CHANGE!   
2. assign WVALID_mask = mask_pre;          

Hello,

Slave will then send wready (telling the CPU it is ready to accept more data).

This is not right. It has possibility of deadlock.  The wvalid and wready should be independent.

Whereas we are working on the contrary.

No, we consider two cases which wvalid is faster than wready and wready is faster than wvalid.

wready is being masked and wvalid is being sent to the slave.

I'm sorry. You are right.
assign WVALID_mask = mask_pre;
would be also
assign WVALID_mask = FIRST_WDATA_MASK | mask_pre;

Best regards,

Yasuhiko Koumoto.

Sir

It does not work .

Regards

Preet