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can we delay read and write transactions(axi4) by providing delay in register slice?

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Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

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    Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself

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    Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself

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