Hi all,
I am using MPU of Cortex-R5, in doing so when writing to Base Register, via standard CP15 access. (MCR p15, 0, Rd, c6, c1, 0) it randomly causes Prefetch Abort Exception, i.e. sometimes it works fine aswell. and IFSR shows PERMISSION type fault.
The regions' base address are aligned to their respective sizes.
So, what can be a possible reason for this behaviour ?
Thanks in advance.
Hi Uali,
A permission fault would suggest that the MPU is preventing access to a region of code. For instance if the MCR instruction is in a region that is set to Privilege access only, but you try branching to this location to execute it from user mode, then it would cause this sort of fault. (If the MCR instruction is in a region that _is_ executable in user mode and you call it from user mode, it should cause an undefined instruction abort)
However if you call the function from a privileged mode (such as sys, svc, IRQ or FIQ) then it should work fine. Is your MCR within a function that is called from different execution modes? When the fault occurs, what instruction is the fault status register pointing to?
regards,
Jon
Thanks a lot Jon. You are very right. But I am calling the MCR instruction from sys-Mode. And when the fault occurs IFSR points to the MCR instruction that causes the the abort.
Any other possible reason for this strange behaviour.
Regards,Umar
Hi Umar,
Even in Sys mode, it is possible have a region that is not accessible (for instance it could be set to XN for execute never, or the access permissions could be set not to allow access to any privilege). You can see all the different options here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbcdeca.html
If you are still having problems, can you share how you have your MPU set up for the region containing this instruction? ie base address, size of MPU region, permissions, and what the program counter is of the instruction that is causing the abort?