Hi all,
I am using MPU of Cortex-R5, in doing so when writing to Base Register, via standard CP15 access. (MCR p15, 0, Rd, c6, c1, 0) it randomly causes Prefetch Abort Exception, i.e. sometimes it works fine aswell. and IFSR shows PERMISSION type fault.
The regions' base address are aligned to their respective sizes.
So, what can be a possible reason for this behaviour ?
Thanks in advance.
Hi Umar,
Even in Sys mode, it is possible have a region that is not accessible (for instance it could be set to XN for execute never, or the access permissions could be set not to allow access to any privilege). You can see all the different options here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbcdeca.html
If you are still having problems, can you share how you have your MPU set up for the region containing this instruction? ie base address, size of MPU region, permissions, and what the program counter is of the instruction that is causing the abort?
regards,
Jon