ARM Cortex A9 flush cache

Dear Yasuhiko Koumoto,

Difference in execution time are huge during consecutive runs (78ms, 52ms,...).

I believe flushing cache before each run will make it more deterministic.

I can randomly read/write huge data to clear cache contents. But OS may allocate a region of cache space for this operation and thus not clearing all the data in the cache.

Alternatively, measuring maximum value of 'n' runs would make sense to worst case execution time.

I wonder if there is a clean way to bring the execution time more deterministic.

Update:

I found GCC function __builtin___clear_cache(); that flushes only the instruction cache.

Dear Yasuhiko Koumoto,

Difference in execution time are huge during consecutive runs (78ms, 52ms,...).

I believe flushing cache before each run will make it more deterministic.

I can randomly read/write huge data to clear cache contents. But OS may allocate a region of cache space for this operation and thus not clearing all the data in the cache.

Alternatively, measuring maximum value of 'n' runs would make sense to worst case execution time.

I wonder if there is a clean way to bring the execution time more deterministic.

Update:

I found GCC function __builtin___clear_cache(); that flushes only the instruction cache.