I would like to use the TCMRETRY function of your company's ARMV7 chip, but there is little and unclear description of this function in the documentation, so I would like to seek assistance.May I ask how to use this feature and how to implement it specifically?
Hello, maybe I didn't express myself clearly.What I mean is that I understand the function of this signal, but in actual chip hardware design, how should this signal be coordinated with external ECC.For example, when I detect that the ECC check of the read data returned by TCM at address 0x010 fails, I will raise the TCMretry signal.What I want to know is how the core will react when it receives the TCMretry signal at this time. Will Core re initiate access to address 0x10?Also, if the access request to TCM is an instruction received by an external AHBS port, is the RDATA returned by AHBS incorrect data or the data obtained after the core re initiates the access?If possible, could you provide a detailed timing diagram for this function, as the manual only covers how to reverse the signal timing diagram, and does not introduce the response of the core after reversing the error