R52 interface restriction - cache line boundary alignment

Hi ...

In the Cortex-R5 TRM, there are some restrictions for the AXI. 

Such as, no transaction ever crosses a 32-byte boundary in memory for AXI transfer.

Is there any restriction for Cortex-R52 ?

Per our test of Cortex-R52, for the same code, if the code cross two cache line address range will spend much more time than within one cache line address range when I cache is disabled.

BR

Grace

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  • Hi Grace,

    I went through R52 TRM, and not found any words about AXIM alignment restrict (guess you had do the same thing already); thus my guess is R52 has no such restrict. 

    The reason why you see code spend more time if the code cross the cache line when I-Cache disabled, guess maybe R52 issue cross 32-btyes transfer but fabric may split them to two aligned xfer thus CPU suffering some more penalty. 

    B.R

    Jerry

Reply
  • Hi Grace,

    I went through R52 TRM, and not found any words about AXIM alignment restrict (guess you had do the same thing already); thus my guess is R52 has no such restrict. 

    The reason why you see code spend more time if the code cross the cache line when I-Cache disabled, guess maybe R52 issue cross 32-btyes transfer but fabric may split them to two aligned xfer thus CPU suffering some more penalty. 

    B.R

    Jerry

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