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When GICD_IERRR bit set ?

Namu

Hi,

I am using GIC600. I found one unusal thing related GICD_IERRR bit. During bootup sometime i saw GICD_IERRR bit is set. I am checking all GICD_IERRR bit before configuring distributor, CPU interface and redistributor.GICD_IERRR bit indicate SPI RAM error only or it indicate different error also?

Thank you in advance for your time and support

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  • 0 Arm Employee Badge

    No, it is not SPI RAM.  

    SPI is a concept defined by Arm GIC specification, which means Shared Peripheral Interrupt.

    <quote>

    The GIC can deal with four different types of interrupt sources:

    • Shared Peripheral Interrupt (SPI). Peripheral interrupts that can be delivered to any connected core.
    • Private Peripheral Interrupt (PPI). Peripheral interrupts that are private to one core. An example of a PPI is an interrupt from the Generic Timer.
    • Software Generated Interrupt (SGI). SGIs are typically used for inter-processor communication and are generated by a write to an SGI register in the GIC.
    • Locality-specific Peripheral Interrupt (LPI). LPIs were first introduced in GICv3 and have a very different programing model to the other three types of interrupt. The configuration of LPIs is covered in the Arm CoreLink Generic Interrupt Controller v3 and v4: Locality-specific Peripheral Interrupts guide.

    </quote>

    For details, please refer to: developer.arm.com/.../Arm-GIC-fundamentals

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  • 0 Arm Employee Badge

    No, it is not SPI RAM.  

    SPI is a concept defined by Arm GIC specification, which means Shared Peripheral Interrupt.

    <quote>

    The GIC can deal with four different types of interrupt sources:

    • Shared Peripheral Interrupt (SPI). Peripheral interrupts that can be delivered to any connected core.
    • Private Peripheral Interrupt (PPI). Peripheral interrupts that are private to one core. An example of a PPI is an interrupt from the Generic Timer.
    • Software Generated Interrupt (SGI). SGIs are typically used for inter-processor communication and are generated by a write to an SGI register in the GIC.
    • Locality-specific Peripheral Interrupt (LPI). LPIs were first introduced in GICv3 and have a very different programing model to the other three types of interrupt. The configuration of LPIs is covered in the Arm CoreLink Generic Interrupt Controller v3 and v4: Locality-specific Peripheral Interrupts guide.

    </quote>

    For details, please refer to: developer.arm.com/.../Arm-GIC-fundamentals

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