Hi Arm, We use Cortex R5 and Cortex M33 in our embedded system, and there’s a controller between CPUs and PSRAMs. When CPU accesses PSRAM, controller will check whether the access is permitted, and if it’s not permitted, controller will return error response signal to CPU. In receiving error response tests, CPU goes into exception when read operation triggers errors, but works normally when write operation triggers errors. So what causes the difference between CPU behavior when CPU receives error response signal during reading or writing? And how CPU deal with error response signal in it’s internals?