Hi Arm, We use Cortex R5 and Cortex M33 in our embedded system, and there’s a controller between CPUs and PSRAMs. When CPU accesses PSRAM, controller will check whether the access is permitted, and if it’s not permitted, controller will return error response signal to CPU. In receiving error response tests, CPU goes into exception when read operation triggers errors, but works normally when write operation triggers errors. So what causes the difference between CPU behavior when CPU receives error response signal during reading or writing? And how CPU deal with error response signal in it’s internals?
Apologies for the delay in anyone responding to this question. The Community Help forum is for general questions about using the Arm Community. I have moved your question to the Architectures and Processors forum where someone may be able to help you.
Arm Community Manager
The description you gave is too vague to judge.
Some suggestions for you to debug further:
1) You can check what's the Error type when Read Errors occur or Write Errors occur. Then you can read the processor TRM to check the details for the Error Types.
2) Read Error or Write Error are both triggered by the same processor? Or Read Error is triggered by Cortex-R5 and Write Error is triggered by Cortex-M33? or vice versa? Anyway, Cortex-R can have different behavior from Cortex-M.
3) When you say "but works normally when write operation triggers errors", do you have suitable Exception Handler to deal with this Error Type? Or actually the "works normally " code is running in a higher privilege level ?