When using the CPUs of the cortex-A72, we find illegal instructions. However, the system finds that no error is detected in the DDR ECC. We suspect that the fault is caused by bit flip in the L1/L2 cache. Currently, by reading the register L2CTLR_EL1 of the A72, where the value of the L2CTLR_EL1 register is 0x01C00082, we find that the cache of the L1/L2 is not enabled, where the bit21 of the L2CTL_EL1 is the L1/L2 cache ECC enabling bit. Why A72 core's L1/L2 cache ECC is not enabled? If we enable bit21, is there any other risk?
Hello
I have moved your question to the Architectures and Processors forum where someone may be able to help you.
Many thanks
Oli
Arm Community team
hello，Many thanks